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K4N26323AE-GC
128M GDDR2 SDRAM
128Mbit GDDR2 SDRAM
1M x 32Bit x 4 Banks GDDR2 SDRAM with Differential Data Strobe and DLL
Revision 1.7 January 2003
Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Revision History
Revision 1.7 (January 23, 2003)
- Changed the device name from GDDR-II to GDDR2
128M GDDR2 SDRAM
Revision 1.6 (December 18, 2002)
- Typo corrected
Revision 1.5 (December 4, 2002)
- Typo corrected
Revision 1.4 (November 12, 2002)
- Changed the device name from DDR-II to GDDR-II - Typo corrected
Revision 1.3 (November 8, 2002)
- Typo corrected
Revision 1.2 (November 5, 2002)
- Typo corrected - Changed the Icc6 from 3mA to 7mA
Revision 1.1 (October 30, 2002)
- Typo corrected
Revision 1.0 (September 30, 2002)
- Changed tCK(max) from 4.5ns to 4.0ns
Revision 0.7 (September 12, 2002)
- Added IBIS curve in the spec - Defined DC spec - Typo corrected - Defined Burst Write with AP (AL=0) Table. - Defined On-die Termination Status of 2Banks System Table. - Changed CIN1,CIN2,CIN3,Cout and CiN4 from 3.5pF to 3.0pF - Removed CL(Cas Latency) 8 from the spec - Changed VDD form 2.5V + 5% to 2.5V + 0.1V - Changed speed bin from 500/400/333MHz to 500/450/400MHz - Changed EMRS table
Revision 0.6 (February 28, 2002)
- Changed WL(write latency) from RL(read latency) -1 to AL(additive latency) +1 - Changed tIH/tSS during EMRS from 5ns to 0.5tCK - Changed tRCDWR - Changed package ball location of CK, /CK, CKE
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Revision 0.5 (January 2002)
- Eliminated DLLEN pin - Power-up sequence
128M GDDR2 SDRAM
Revision 0.4 (January 2002)
- Changed EMRS Table - Changed Self-Refresh exit mode - Changed On-die Termination Control - Changed OCD Control method - Power-up sequence
Revision 0.3 (December 2001)
- Noted the ball names changed from DDR-1 and exchanged DQS and /DQS ball location. - Added On-die termination control - Changed OCD align mode entry / exit timing - Added target value of Data & DQS input/output capacitance(DQ0~DQ31) - Added Table for auto precharge control - Typo corrected.
Revision 0.2 (November 2001)
- Data Strobe Scheme is changed from DQS separation of Read DQS, Write DQS to Differential and Bi-directional DQS - OCD adjustment - Controlled DQ is changed from DQ0, WDQS2 to DQ23, DQS2 and /DQS2
Revision 0.1 (October 2001)
- Data Strobe Scheme is changed from Bi-directional DQS to DQS separation to Read DQS, Write DQS - Package Ball layout is changed for mirror package. - OCD adjustment Controlled DQ is changed from DQ0, DQS0 to DQ23, WDQS2 - Added DM descriptions - 1bank, 2bank system - Added System Selection mode in EMRS table.
Revision 0.0 (August 2001)
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
1M x 32Bit x 4 Banks GDDR2 Synchronous DRAM with Differential Data Strobe FEATURES
* 2.5V + 0.1V power supply for device operation * 1.8V + 0.1V power supply for I/O interface * On-Die Termination for all inputs except CKE,ZQ * Output Driver Strength adjustment by EMRS * SSTL_18 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs - CAS latency : 5, 6, 7 (clock) - Burst length : 4 only - Burst type : sequential only * Additive latency (AL): 0,1(clock) * Read latency(RL) : CL+AL * Write latency(WL) : AL+1
128M GDDR2 SDRAM
* Differential Data Strobes for Data-in, Date out ; - 4 DQS and /DQS(one differential strobe per byte) - Single Data Strobes by EMRS. * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & Self refresh * 32ms refresh period (4K cycle) (16ms is under consideration) * 144 Ball FBGA * Maximum clock frequency up to 500MHz * Maximum data rate up to 1Gbps/pin * DLL for Address, CMD and outputs
ORDERING INFORMATION
Part NO. K4N26323AE-GC20 K4N26323AE-GC22 K4N26323AE-GC25 Max Freq. 500MHz 450MHz 400MHz Max Data Rate 1000Mbps/pin 900Mbps/pin 800Mbps/pin SSTL_18 144 Ball FBGA Interface Package
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank GDDR2 SDRAM
The 4Mx32 GDDR2 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,976 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
PIN CONFIGURATION
Normal Package (Top View)
2 B C D E F G H J K L M N
DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ20 DQ21 DQ23 VREF A0
128M GDDR2 SDRAM
3
/DQS0 DM0 DQ5 VDDQ DQ16 DQ18 /DQS2 DM2 DQ22 A3 A2 A1
4
VSSQ VDDQ VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD A10 A11
5
DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS /RAS BA0
6
DQ2 DQ1 VSSQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS RFU2 NC /CAS
7
DQ0 VDDQ VDD VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VDD CKE CK
8
DQ31 VDDQ VDD VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VDD NC /CK
9
DQ29 DQ30 VSSQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS RFU1 ZQ /WE
10
DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS /CS BA1
11
VSSQ VDDQ VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD A9 A8/AP
12
/DQS3 DM3 DQ26 VDDQ DQ15 DQ13 /DQS1 DM1 DQ9 A4 A5 A6
13
DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ11 DQ10 DQ8 VREF A7
NOTE : 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. (M,13) VREF for CMD and ADDRESS 4. (M,2) VREF for Data input
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
PIN CONFIGURATION
Mirror Package (Top View)
128M GDDR2 SDRAM
2 B C D E F G H J K L M N
DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ11 DQ10 DQ8 VREF A7
3
/DQS3 DM3 DQ26 VDDQ DQ15 DQ13 /DQS1 DM1 DQ9 A4 A5 A6
4
VSSQ VDDQ VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD A9 A8/AP
5
DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS /CS BA1
6
DQ29 DQ30 VSSQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS RFU1 ZQ /WE
7
DQ31 VDDQ VDD VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VDD NC /CK
8
DQ0 VDDQ VDD VSS NC, VSS NC, VSS NC, VSS NC, VSS VSS VDD CKE CK
9
DQ2 DQ1 VSSQ VSSQ NC, VSS NC, VSS NC, VSS NC, VSS VSS RFU2 NC /CAS
10
DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS /RAS BA0
11
VSSQ VDDQ VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD A10 A11
12
/DQS0 DM0 DQ5 VDDQ DQ16 DQ18 /DQS2 DM2 DQ22 A3 A2 A1
13
DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ20 DQ21 DQ23 VREF A0
* Under consideration
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK, CK Type Input Function
128M GDDR2 SDRAM
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during Mode Register Set commands.
CKE
Input
CS RAS, CAS, WE DM0 ~DM3 BA0, BA1
Input Input
Input
Input
A0 A11
Input
DQ
Input/ Data Input/ Output: Bi-directional data bus. Output Data Strobe: output with read data, input with write data for source synchronous operation.Edge-aligned with read data, centered in write data.
DQS0~ DQS3 DQS0~ DQS3
DQS Scheme Input/ Output DQS0, DQS0 DQS1, DQS1 DQS2, DQS2 DQS3, DQS3
Differential DQS per byte DQS0 for DQ0-DQ7 DQS1 for DQ8-DQ15 DQS2 for DQ16-DQ23 DQS3 for DQ24-DQ31
NC/ RFU VDDQ VSSQ VDD VSS VREF ZQ
No Connect: No internal electrical connection is present. Supply DQ Power Supply: 1.8V 0.1V Supply DQ Ground Supply Power Supply: 2.5V 0.1V Supply Ground Supply Reference voltage: half Vddq , 2 Pins : (M,2) for Data input , (M,13) for CMD and ADDRESS input Resistor connection pin for On-die termination. The value of Resistor = 2 X (target value (Rterm) of termination resistance of DQ pin of each chip)
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
DQS , DQS
128M GDDR2 SDRAM
CK, CK
Input Buffer
32
Input DLL
Input Buffer I/O Control LWE LDMi
Bank Select
Data Input Register Serial to parallel
128
1M x 32 Output Buffer 4-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 1M x 32 1M x 32 1M x 32
128 32
x32
DQi
Address Register
iCK
ADDR
Column Decoder LCBR LRAS Col. Buffer
Latency & Burst Length Strobe Gen. DQS, DQS
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR
Output DLL
CK,CK
LDMi
Timing Register
iCK
CKE
CS
RAS
CAS
WE
DMi
* iCK : internal clock
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
FUNTIONAL DESCRIPTION Simplified State Diagram
Power Applied Power On DLL Enable
128M GDDR2 SDRAM
Precharge PREALL
Self Refresh REFS REFSX
MRS EMRS
MRS
Idle
REFA
Auto Refresh
CKEL CKEH
Active Power Down CKEH CKEL
ACT
Precharge Power Down
Row Active Write Write A Write Write Read A Read
Read
Read
Write A Read A Write A PRE PRE PRE
Read A
Read A
PRE
Precharge PREALL Automatic Sequence Command Sequence
PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh
CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Power-Up Sequence
128M GDDR2 SDRAM
GDDR2 SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Power Up Sequence - Apply Power and Keep CKE at low state. (All other inputs may be undefined) - Apply VDD before VDDQ. - Apply VDDQ before VREF. - Start low frequency clock(100MHz) and maintain stable condition for minimum 200us. - The minimum of 200us after stable power and clock (CK, /CK), apply NOP and take CKE to be high. - Issue precharge command for all banks of the device ( tS/tH =0.5tCK). - Issue EMRS command to initialize DRAM with DLL OFF and On-die Termination OFF( tS/tH=0.5tCK) . BA1 BA0 A11
0 1 0
A10
X
A9
A8
X
A7
A6
0
A5
X
A4
A3
0
A2
0
A1
X
A0
Address Bus Extended Mode Register
- Issue EMRS command to control DLL and decide on-die termination state. Within 100 clocks after issuing EMRS command for DLL on, stable high frequency clock should be supplied to DRAM. BA1 BA0 A11
0 1 0
A10
V
A9
A8
V
A7
A6
1
A5
V
A4
A3
V
A2
V
A1
V
A0
Address Bus Extended Mode Register
(V=Valid value) - The additional 1ms clock cycles are required to lock the DLL and determine value of on-die termination after issuing EMRS command or supplying stable clock from a controller. Apply NOP during Locking DLL to protect invalid command. - Issue precharge command for all banks of the device. - Issue EMRS command - Issue at least 10 or more Auto refresh command to update the value of on-die termination. - Issue a MRS command to initialize the mode register. - Issue any command.
Power up & Initialization Sequence
CKE
200 us < 100tCK 1ms
CK,CK
low freq. (> 100Mhz) stable high freq.
tRP
tRP
tMRD
tRFC
tRFC
4 Clock min.
CMD
~
NOP
Precharge all banks
NOP
EMRS1
NOP
EMRS2
NOP
Precharge all banks
EMRS 1st Auto Refresh
10th Auto Refresh
MRS
Any Command
* Minimum setup/hold time tIS, tIHmin = 0.5tCK at the Low frequency without DLL * Within 100 tCK after issuing EMRS2, PLL(DLL) of controller should be enabled. * During changing clock frequency, the changing rate should be smaller than 100ps/30tCK
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
MODE REGISTER SET(MRS)
128M GDDR2 SDRAM
The mode register stores the data for controlling the various operating modes of GDDR2 SDRAM. It programs CAS latency, addressing mode, test mode and various vendor specific options to make GDDR2 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR2 SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum four clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is used for test mode. A9 ~ A11 are used for tWR. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
*
tWR
0
TM
CAS Latency
BT
Burst Length
*1
Mode Register
Test Mode A7 BA0 0 1 An ~ A0 MRS EMRS 0 1 mode Normal Test
Burst Length A2 0 A1 1 0
A0
Burst Length 4
Burst Type A3 0 Burst Type Sequential
tWR A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 MRS Select Reserved Reserved 3 4 5 Reserved Reserved Reserved
CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved Reserved Reserved Reserved 5 6 7
*1. BL 4, Sequential Only
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
EXTENDED MODE REGISTER SET(EMRS)
128M GDDR2 SDRAM
The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Four clock cycles are required to complete the write operation in the extended mode register. 8 kinds of the output driver strength are supported by EMRS (A9, A8, A7) code. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
Address Bus Extended Mode Register
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
1
0
ODT.R
Output driver strength
DLL
DQS
A.L
ODT control
ODT option
DLL *1 BA0 0 1 An ~ A0 MRS EMRS DQS*2 A5 ODT of DQs @ RD A10 0 1 mode ON OFF Additive Latency A4 0 1 Latency 0 1 0 1 DQS Differential Single
A6 0 1 DLL DLLOFF DLLON
On-die Termination option *1 for CMD & ADDR A1 0 0 1 1 A0 0 1 0 1 Value OFF X1 X2 X4
OFF : On-die Termination of CMD and ADDR pins on DRAM is off X1 : On-die Termination value of CMD and ADD pins are same as the value of DQ X2 : 2 times of the value of DQ X4 : 4 times of the value of DQ
Output Driver Strength Option A9 0 0 0 0 1 1 1 1 A8 0 0 1 1 0 0 1 1 A7 0 1 0 1 0 1 0 1 Ron[ohm] 60 55 50 45 40 35 30 25
On-Die Termination Mode *1 A3 0 0 1 1 A2 0 1 0 1 Value ODT OFF ODT Cal. ON Rterm=60 Rterm=120
*1. DLL control,ODT control,and ODT option command should be issued at low frequency clock(<100Mhz) with tIS/tIH=0.5tCK *2. When single DQS is selected, 4 /DQS pins should be connected to VREF.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
DQS
500MHz Differential DQS 450MHZ Differential DQS
128M GDDR2 SDRAM
400MHz Differential DQS Single DQS
* To support existing DDR-I user , single DQS is supported under 400MHz by EMRS option, When single DQS is selected, 4 /DQS pins should be connected to VREF.
Differntial DQS Timing (CL5, BL4)
0 CK, CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CMD DQS DQS
READ
WRITE
DQ
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
Single DQS Timing (CL5, BL4)
0 CK, CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CMD DQS
READ
WRITE
DQS DQ
Vref Level
Dout0 Dout1 Dout2 Dout3
Din0 Din1 Din2 Din3
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Bank Activate Command
128M GDDR2 SDRAM
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the GDDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of (0,1) are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC), which is equal to tRAS + tRP. The minimum time interval between Bank Activate commands, Bank 0,1, 2, 3 (in any order), is the Bank to Bank delay time (tRRD).
Bank Activate Command Cycle : CL=7, tRCD=9, AL=1, tRP=8, tRRD=5, tCCD=2, tRAS=19
0 CK, CK
tRRD = 5
1
2
3
4
5
8
9
13
14
15
16
17
18
19
24
27
CMD
Bank A Activate
Bank B Activate
Post CAS Read A
Post CAS Read B Additive Latency
Bank A Precharge
Bank B Precharge
Bank A Activate
Additive Latency tRCD = 9
tRP = 8
DQS
tRAS = 19 CAS Latency
Dout0 Dout1 Dou2 Dout3
DQ
internal Read Command Start (Bank A)
internal Read Command Start (Bank B)
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. The WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). A new burst access must not interrupt the previous 4 bit burst operation. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
Write Latency
The Write Latency(WL) is always defined as AL(Additive Latency)+1 where Read Latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL).
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Posted CAS
128M GDDR2 SDRAM
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in GDDR2 SDRAM. In this operation, the GDDR2 SDRAM allows a CAS read or write command to be issued tRCDmin or 1 tCK earlier than tRCDmin after the RAS bank activate command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMRS.
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank [AL = 1, tRCD = 9, CL = 7, RL = (AL + CL) = 8, WL = (AL + 1) = 2]
0 CK, CK CMD
Active A-Bank
7
8
13
14
15
16
17
18
19
20
21
22
23
Read A-Bank tRL
Write A-Bank
DQS
tWL
DQ
Dout0 Dout1
Dou2 Dout3
Din0
Din1
Din2
Din3
tHZ
tHZ > 1 tCK
Example 2
Read followed by a write to the same bank [AL = 0, tRCD = 9, CL = 7, RL = (AL + CL) = 7, WL = (AL + 1) = 1]
0 CK, CK CMD
Active A-Bank
1
8
9
14
15
16
17
18
19
20
21
22
Read A-Bank
RL
Write A-Bank
DQS
tRCD
tWL
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
DQ
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Burst Read Command
128M GDDR2 SDRAM
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the Extended Mode Register Set (EMRS).
Burst Read Operation: RL = 8 (AL = 1, CL = 7)
0 1 2 7 8 9 10 11 12 13
CK, CK CMD
Posted CAS READ A NOP Post CAS Read A NOP NOP NOP NOP NOP NOP NOP
DQS
tDQSCK AL =1 RL = 8 CL = 7
DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 DOUTA7
DQs
internal Read Command Start (Bank A)
Burst Read Operation: RL = 7 (AL = 0 and CL = 7)
0 1 2 7 8 9 10 11 12 13
CK, CK
Post CAS Read A
CMD
Posted CAS READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
tDQSCK CL = 7 RL = 7
DQs
DOUTA0 DOUTA1 DOUTA2 DOUTA3 DOUTA4 DOUTA5 DOUTA6 DOUTA7
internal Read Command Start (Bank A)
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
Burst Read followed by Burst Write : AL = 1, CL = 7, RL = 8, WL = (AL+1) = 2
0 CK, CK
Post CAS Write A
1
6
7
8
9
10
11
12
13
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
RL =8 tHZ
DQ's
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DINA0
DINA1
DINA2
DINA3
WL = 2
tHZ > 1 tCK
Seamless Burst Read Operation: CL = 7, AL = 1, RL = 8
0 CK, CK 1 2 7 8 9 10 11
CMD
Post CAS READ A0
NOP
Post CAS READ A4
NOP
NOP
NOP
NOP
NOP
NOP
DQS
AL = 1 RL = 8 CL =7
DQ's
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
The seamless burst read operation is supported by enabling a read command at every other clock. This operation is allowed regardless of same or different banks as long as the banks are activated.
- 17 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Burst Write Operation
128M GDDR2 SDRAM
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by an Additive Latency(AL) plus one and is equal to (AL + 1). The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the clock and at the first falling edge of the clock. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the clock until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR).
Burst Write Operation : AL= 1, CL = 7, WL = 2, tWR = 5
0 CK, CK 1 2 3 4 5 6 9
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
DQS
WL =2
DQ
DINA0 DINA1 DINA2
DINA3 tWR = 5
Burst Write followed by Burst Read : RL = 7 (AL=0, CL=7), WL = 1, tCDLR = 4
0 CK, CK
Write to Read Latency = WL + 2 + t CDLR =7
1
2
3
7
14
15
16
CMD
Post CAS WRITE A
NOP
NOP
NOP
NOP
Post CAS READ A
NOP
NOP
NOP
NOP
NOP
DQS
CL = 7 tWL = 1 > = tCDLR
DQ
DINA0 DINA1 DINA2 DINA3
DOUTA0 DOUTA1 DOUTA2 DOUTA3
The minimum number of clock from the burst write command to the burst read command is WL+2+a write-toread-turn-around-time(tCDLR).
- 18 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
Seamless Burst Write Operation : AL = 1, CL = 7, WL = AL + 1 = 2
0 CK, CK CMD
Post CAS WRITE A Post CAS WRITE B
1
2
3
7
8
9
10
11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
WL = 2
DQ's
DINA0
DINA1
DINA2
DINA3
DINB0
DINB1
DINB2
DINB3
The seamless burst write operation is supported by enabling a write command every other clock. This operation is allowed regardless of same or different banks as long as the banks are activated
- 19 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Precharge Command
128M GDDR2 SDRAM
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A8, BA0 and BA1 are used to define which bank to precharge when the command is issued.
Bank Selection for Precharge by Address Bits
A8 LOW LOW LOW LOW HIGH BA1 LOW LOW HIGH HIGH DON'T CARE BA0 LOW HIGH LOW HIGH DON'T CARE Precharged Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All Banks 0 ~ 3
Burst Read Operation Followed by Precharge
For the earliest possible precharge, the precharge command may be issued on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.
Burst Read Operation Followed by Precharge: RL = 7 (AL=0, CL=7), tRP= 8
0 CK, CK
Post CAS READ A Bank A Active
2
3
4
5
6
7
8
9
10
11
CMD
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
> = tRP CL =7
DQ
DOUTA0 DOUTA1 DOUTA2
DOUTA3
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
Burst Read Operation Followed by Precharge: RL = 8 (AL=1, CL=7, tRP =8)
0 CK, CK 3 7 8 9 10 11 12 13
CMD
Posted CAS READ A
Precharge A
NOP
NOP
NOP
NOP
Bank A Activate
NOP
NOP
DQS
> = tRP RL = 8
DQ's
DOUTA0 DOUTA1 DOUTA2 DOUTA3
Burst Write followed by Precharge
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay, as GDDR2 SDRAM does not support any burst interrupt operation.
Burst Write followed by Precharge: AL = 1, CL = 7, WL = AL + 1 = 2, tWR = 5
0 CK, CK 1 2 3 4 5 6 9
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
DQS
WL = 2 tWR = 5
DINA0 DINA1 DINA2 DINA3
DQ's
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
DM FUNCTION
128M GDDR2 SDRAM
The DDR SDRAM has a Data mask function that can be used in conjunction with data Write cycle only, not Read cycle. When the Data Mask is activated (DM high) during write operation the write data is masked immediately (DM to Data-mask Latency is zero). DM must be issued at the rising edge or the falling edge of Data Strobe instead of a clock edge.
0 CK, CK 1 2 3 4 5 6 9
CMD DQS
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
WL = 2
tWR = 5
DINA0 DINA1 DINA2 DINA3
DQ's DM
masked by DM=H
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the GDDR2 SDRAM, the CAS timing accepts one extra address, column address A8, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A8 is low when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A8 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Burst Read with Auto Precharge
128M GDDR2 SDRAM
If A8 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The GDDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2)cycles later from the read with Auto Precharge command, when tRAS(min) is satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto Precharge operation will be delayed until tRAS(min) is satisfied. A new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
When the Read with Auto-Precharge command is issued, new command (Read, Read with Auto Precharge or precharge) of same bank can be asserted tCCD=2 clock cycles later.
Burst Read with Auto Precharge Followed by Same Bank Activation : RL = 8 (AL = 1, CL = 7, internal tRP = 8)
0 3 CK, CK
A8 = 1 Post CAS READ A
7
8
9
10
11
12
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Activate
NOP
Auto Precharge Begins
DQS > = tRP
RL = 8
DQ's
DOUTA0 DOUTA1 DOUTA2 DOUTA3
Burst Read with Auto Precharge (AL=0)
Asserted command READ READ with Auto Precharge Active Precharge For same bank 1 Illegal Illegal Illegal Illegal 2 Legal Legal Illegal Legal 3 Illegal Illegal Illegal Illegal 4 Illegal Illegal Illegal Illegal 1 Illegal Illegal Legal Legal For different bank 2 Legal Legal Legal Legal 3 Legal Legal Legal Legal 4 Legal Legal Legal Legal
*When AL(Additive Latency) is 1, a precharge command for same bank can be issued at 3th cycle only and others are same with AL=0.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Burst Write with Auto-Precharge
128M GDDR2 SDRAM
If A8 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The GDDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). Interruption of the Write with Auto-Precharge function is prohibited. Active command of same bank can be issued WL+tWR+tRP+BL/2 cycles later from the Write with Auto-Precharge command. The bank undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst Write with Auto-Precharge : AL = 0, WL = 1, tWR = 5, tRP=8(for the same bank)
0 CK, CK
A8 = 1
1
2
3
4
7
8
9
16
CMD
Post CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Auto Precharge Begins
NOP
Bank A Active
DQS
WL=1
> = tWR
DINA0 DINA1 DINA2 DINA3
> = tRP
DQs
Burst Write with Auto-Precharge (AL=0)
Asserted command WRITE WRITE with Auto Precharge READ READ with Auto Precharge Active Precharge All Bank Precharge For same bank 1~7 Illegal Illegal Illegal Illegal Illegal Illegal Illegal 8 Illegal Illegal Illegal Illegal Illegal Illegal Legal 9 ~ 15 Illegal Illegal Illegal Illegal Illegal Illegal Legal 16 Illegal Illegal Illegal Illegal Legal Illegal Legal 1 Illegal Illegal Illegal Illegal Legal Legal For different bank 2~6 Legal Legal Illegal Illegal Legal Legal 7 Legal Legal Legal Legal Legal Legal
*When AL(Additive Latency) is 1, a active command for same bank can be issued from 17th cycle , a READ or READ with Auto Precharge command for different bank can be issued from 8th cycle and others are same with AL=0. * All Bank Precharge command can be issued from 8th cycle.
- 24 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Automatic Refresh Command (CAS Before RAS Refresh)
128M GDDR2 SDRAM
When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the GDDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the GDDR2 SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the Auto Refresh cycle time (tRFC).
CK, CK CKE
High > = tRP > = tRFC
CMD
Precharge
NOP
CBR
Bank Activate
NOP
NOP
Self Refresh Command
The GDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the Self Refresh Command is registered, CKE must be held low to keep the device in Self Refresh mode and NOP command should be issued or CS should be held high to ensure stable self refresh operation for next four cycles after the Self Refresh Command. When the GDDR2 SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. After CKE is brought high, an internal timer is started to insure CKE is held high for approximately 10ns before registering the Self Refresh exit command. The purpose of this circuit is to filter out noise glitches on the CKE input which may cause the GDDR2 SDRAM to erroneously exit Self Refresh operation. Once the Self Refresh exit command is registered, a delay equal or longer than the tXSA (>20000 tck) must be satisfied before any command can be issued to the device. CKE must remain high for the entire Self Refresh exit period (tXSA > 20000tCK) and commands must be gated off with CS held high. Alternatively, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval. (See Figure.)
CK, CK
tXSA (> 20000tCK)
CKE
> = 4clk CMD
Self Refresh NOP NOP ANY Command
*After self refresh entry, NOP or chip deselect command should be issued during more than 4 cycles and chip deselet command should be issued for tXSA after self refresh exit.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Power-Down
128M GDDR2 SDRAM
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. During 4 cycles after power down mode issued, NOP should be issued or CS must be held high. In Power Down mode, CKE Low and a stable clock signal must be maintained at the inputs of the GDDR2 SDRAM, and all other input signals are "Don't Care" except first 4 cycles after power down mode issued. Power-down duration is limited by the refresh requirements of the device. The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or CS hold high). A valid, executable command may be applied four clock cycles later.
Power Down
CK, CK tIS tIS 4tck VALID NOP*1 NOP NOP Exit power down mode Enter Power Down mode ( Read or Write operation must not be in progress) Don't Care NOP NOP NOP VALID
CKE
CMD No column access in progress
*1. NOP or CS held high should be issued more than 4 cycles.
*CL + 2tCK after read or CL after last data in, a power-down command can be issued.
Burst Interruption
Interruption of a burst read or write cycle is prohibited.
No Operation Command
The No Operation Command should be used in cases when the GDDR2 SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the GDDR2 SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don't cares.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
On-Die Termination
128M GDDR2 SDRAM
All pins except ZQ, CKE Pins adopt on-die termination to improve signal integrity of channel. The On-Die Termination should be controlled by EMRS command at low frequency clock (<100Mhz). The On-Die Termination control command should be issued before issuing DLLON command by EMRS or simultaneously to guarantee stable channel condition of /CK and CK pins. If A3, A2 = 0, 0, the On-Die Termination of all pins will be deactivated. If A3, A2 = 0, 1, the On-Die Termination will be self-calibrated by detecting the external Resistor on ZQ pin. If A3, A2 = 1, 0, the value of the On-Die Termination of CK, /CK, 32 DQ's, 4 DM's, 4 /DQS's and 4DQS pins will be the fixed value, 60ohm. If A3, A2 = 1, 1, the value of the On-Die Termination of CK, /CK, 32 DQ's, 4 DM's, 4 /DQS's and 4DQS pins will be the fixed value,120ohm. If A3, A2 = 0, 1 is issued by EMRS, the value of the on-die termination of each pin is determined by monitoring the value of a external resistor which is connected between ZQ pin and VSSQ, and updated every CBR refresh cycle to compensate variation of voltage and temperature. The value of On-Die Termination of CMD and ADD (/RAS, /CAS, /WE, /CS, BA0, BA1 and A0 ~ A11) pins of each DRAM depend on EMRS code (A1, A0). If A1, A0 = 0, 0 , the On-die Termination of CMD and ADD pins will be deactivated. If A1, A0 = 0, 1, the value of the On-die Termination of CMD and ADD pins will be same value as the value of DQ pins. If A1, A0 = 1, 0, the value of the On-Die Termination of CMD and ADD pins will be two times of the value of DQ pins. If A1, A0 = 1, 1, the value of the On-Die Termination of CMD and ADD pins will be four times of the value of DQ pins. The On-Die Termination for one bank system with self-calibration code (A3, A2 = 0, 1) The value of external resistor (Rref) at external one bank system is 2 times of target termination value of DQ's on channel (Rterm). Then the value of On-Die Termination of CK, /CK, 32 DQ's, 4 DM's, 4 /DQS's and 4DQS pins is half value of the external resistor. The value of On-Die Termination of CMD and ADD ( /RAS, /CAS, /WE, /CS, BA0, BA1 and A0 ~ A11) pins of each DRAM depend on EMRS code (A2, A0). The following figure shows the typical external one bank system having on-die termination.
Block Diagram of 1 Bank System
Front Side DRAMs
CK,/CK ADD /RAS,/CAS,/WE,/CS DM's, DQ'S, DQS's,/DQS's CK,/CK
CK,/CK ADD /RAS,/CAS,/WE,/CS DM's, DQ'S, DQS's,/DQS's CK,/CK ADD /RAS,/CAS,/WE,/CS ZQ ZQ
Rref=2 X Rterm VSSQ
2XRterm VSSQ
Controller
DM's, DQ'S, DQS's,/DQS's CK,/CK /CS /RAS,/CAS,/WE DM's, DQ'S, DQS's,/DQS's CK,/CK
DM's, DQ'S, DQS's,/DQS's CK,/CK ADD /RAS,/CAS,/WE,/CS DM's, DQ'S, DQS's,/DQS's CK,/CK ADD /RAS,/CAS,/WE,/CS ZQ ZQ
2XRterm VSSQ
2XRterm VSSQ Where Rterm is the termination value on charnnel
DM's, DQ'S, DQS's,/DQS's
DM's, DQ'S, DQS's,/DQS's
- 27 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
The On-die Termination on/off status on DRAM is in accompany with DRAM operation mode. Power consumption by On-die termination can be reduced by issuing power down mode.
On-Die Termination (ODT) Status of 1 Bank System
Mode
Self_refresh Power Down Active All banks idle
Pin
All CK, /CK Other pins All CK, /CK, ADD's, CMD DQ's, DQS's, /DQS's, DM's A10=1 CK, /CK, ADD's, CMD, DM,s DQ's, DQS's, /DQS's CK, /CK, ADD's, CMD, DM,s DQ's, DQS's, /DQS's
ODT of DRAM
OFF ON OFF ON ON ON ON OFF ON ON
READ A10=0
* A10 in EMRS code is used for On-Die Termination of DQ's off when Read data comes out
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
The On-die Termination for external two bank system with self-calibration code (A3, A2 = 0, 1)
The external resistor (Rref) is equal to 2X the number of shared DRAM's on one channel X target termination value of DQ channel. The following figure is represented the typical two bank system having on-die termination. 4 DRAM's share one channel for CMD and ADD pins and 2 DRAM's share one channel for DQ's and CLK pins. The external resistor (Rref) is 4 times of target termination value on channel. The On-die Termination value of CK, /CK, 32 DQ's, 4 DM's, 4 /DQS's and 4DQS pins on channel is half value of the external resistor (Rref).
Block Diagram of 2 Banks System
Front Side DRAM's
CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's ZQ 4 X Rterm ZQ 4 X Rterm ZQ 4 X Rterm ZQ 4 X Rterm
Back Side DRAM's
CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK ADD /RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's ZQ 4 X Rterm ZQ 4 X Rterm ZQ 4 X Rterm ZQ Rref = 4 X Rterm
VSSQ
Controller
DM's, DQ's, DQS's, /DQS's CK, /CK /CS
VSSQ
/RAS, /CAS, /WE, /CS DM's, DQ's, DQS's, /DQS's CK, /CK
VSSQ
DM's, DQ's, DQS's, /DQS's
VSSQ
Self-refresh and power down mode in two bank system should be issued for all DRAM's at the same time to keep suitable On-die termination condition on channel. .
Mode Pin M1 Self_refresh Self_refresh Power down Power down M2 Self_refresh Other States Power down Other pins Other States CK, /CK, ADD's, CMD Active DQ's, DQS's, /DQS's, DM's CK, /CK, ADD's, CMD All Banks idle Read CK, /CK, ADD's, CMD A10=0 DQ's, DQS's, /DQS's, DM's CK, /CK, ADD's, CMD A10=1 DQ's, DQS's, /DQS's, DM's Active Read CK, /CK, ADD's, CMD A10=0 DQ's, DQS's, /DQS's, DM's ON ON 1. With these case, the system couldn't have suitable Rterm. Because the On-Die termination value on channel is two times than the target value. ON ON ON OFF ON ON ON ON ON ON A10=1 DQ's, DQS's, /DQS's, DM's ON OFF ON ON ON ON ON ON OFF OFF Illegal All All CK,/CK ON ON
*1
DRAM Remarks M1 OFF M2 OFF Illegal
*1
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
4. Command Truth Table.
CKE Function Previous Cycle H H H H L Exit Self Refresh L Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto-Precharge DM H H H H H H H H H No Operation H H Power Down Mode Entry H L Power Down Mode Exit L 1. 2. 3. 4. H L H H H X L H L H H X H X H X X X X L H H X X X X X X X X H X X X X X X X X X L L L L L L L L X L H L L L H H H H X H H H H H L L L L X H H L L H L L H H X H X X X X X X X X DM X Current Cycle X X H L H CS RAS CAS WE DM
128M GDDR2 SDRAM
BA0/BA1
A11 - A9
A8
A7 - A0
Notes
Mode Register Set Extended Mode Register Set Auto (CBR) Refresh Entry Self Refresh
L L L L H
L L L L X
L L L L X
L L H H X
X X X X X
BA0 = 0 and MRS OP Code BA0 = 1 and EMRS OP Code X X X X BA X BA BA BA BA BA X X X X X X X X X X X X X X X X X X X X X X X X X X X X L H Row Address L H L H X X X X X X X Column Column Column Column X X X X X X X X X X X X X
1 1 1 1 1
1,2 1 1,2 1,2,3, 1,2,3, 1,2,3 1,2,3 6 1 1 1,4,5
1,4,5
All of the GDDR2 SDRAM operations are defined by states of CS, WE, RAS, and CAS at the positive rising edge of the clock. Bank Select (BA0,1), determine which bank is to be operated upon. Burst read or write cycle may not be terminated. The Power Down Mode does not perform any refresh operations, therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. Four clock delay is required for mode entry and exit. 5. If CS is low, then when CKE returns high, no command is registered into the chip for one clock cycle. 6. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
(V=Valid, X=Don't Care, H=Logic High, L=Logic Low)
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
5. Clock Enable (CKE) Truth Table
CKE Current State Previous Cycle H L Self Refresh L L L H L Power Down L L L H H All Banks Idle H H H H Any State other than listed above H L L Current Cycle X H H H L X H H H L H H L L L H L H L CS X H L L X X H L L X H L H L L X X X X X X X X X X H RAS X X H Command CAS X X H Command X X X H Command X X Command X X X X X X X X X X Address X X X H WE X X H BA1, BA0, A11 - A0 X X X Address X X X X Address X
128M GDDR2 SDRAM
Action
Notes
INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle Exit Power Down mode with No Operation ILLEGAL Maintain Power Down Mode Device Deselect Refer to the Current State Truth Table Power Down ILLEGAL Entry Self Refresh Refer to operations in the Current State Truth Table Power Down Power Down Power Down
1 2 2 2
1 2 2 2
3 3
Command except selfrefresh command L X X X X L X X X X H X X X X
4
5
1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied before any command other than self refresh exit. 3. The inputs (BA1, BA0, A11 - A0) depend on the command that is issued. See the Current State Truth Table for more information. 4. The Auto Refresh, Self Refresh Mode, and the Mode Register Set modes can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table.
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS
128M GDDR2 SDRAM
Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 4.5 50
Unit V V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_18 In/Out)
Recommended operating conditions (Voltage referenced to VSS=0V, Tj=0 to 100C)
Parameter
Device Supply voltage Output Supply voltage Reference voltage DC Input logic high voltage DC Input logic low voltage AC Input logic high voltage AC Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current
Symbol
VDD VDDQ VREF VIH (DC) VIL (DC) VIH(AC) VIL(AC) VOH VOL IIL IOL
Min
2.4 1.7 0.49*VDDQ VREF+0.125 -0.30 VREF+0.25 Vtt+0.4 -5 -5
Typ
2.5 1.8 -
Max
2.6 1.9 0.51*VDDQ VDDQ+0.30 VREF-0.125 VREF-0.25 Vtt-0.4 5 5
Unit
V V V V V V V V V uA uA
Note
1 1 2 4 5
6 6 7 7
Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. Output logic high voltage and low voltage is depend on channel condition.(Ract , Ron) 7. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, Tj=0 to 100C)
128M GDDR2 SDRAM
Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank interleaving) Symbol Test Condition -20 ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 ICC7 Burst Lenth=4 tRC tRC(min) -22 540 100 210 100 470 1100 350 7 1400 1300 1180 -25 500 95 190 95 430 990 330 mA mA mA mA mA mA mA mA mA 2 1 Unit Note
IOL=0mA, tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
590 110 230 110 510 1200 370
tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
tCC= tCC(min)
IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated.
tRC tRFC
CKE 0.2V Burst Lenth=4 tRC tRC(min)
IOL=0mA, tCC= tCC(min)
Note : 1. Measured with outputs open & On-Die termination off. 2. Refresh period is 16ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS=0V, VDD=2.5V 0.1V, VDDQ=1.8V 0.1V, Tj=0 to 100 C)
Parameter
Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage ; CK and CK Clock Input Crossing Point Voltage ; CK and CK
Symbol
VIH VIL VID VIX
Min
VREF+0.25 0.5 0.5*VDDQ-0.2
Typ
-
Max
VREF-0.25 VDDQ+0.6 0.5*VDDQ+0.2
Unit
V V V V
Note
1 2 3 4
Note : 1. VIH(Max) = 4.2V. The overshoot voltage duration is < 3ns at VDD. VIH level should be met at the pin of DRAM when ODT=ON. 2. VIL(Min) = -1.5V. The undershoot voltage duration is < 3ns at VSS. VIL level should be met at the pin of DRAM when ODT=ON. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK 4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same DRAM
ODT of DRAM
VDDQ
Controller
Input level should be measured at this point
VSSQ
- 33 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
AC OPERATING TEST CONDITIONS (VDD=2.5V0.1V, Tj= 0 to 100 C)
Parameter Input reference voltage for CK(for single) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.25/VREF-0.25 VREF 1/2 VDDQ See Fig.1 Unit V V V/ns V V V Note
Output
Z0=60
VREF =0.5*VDDQ
CLOAD=10pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=2.5V, TA= 25C, f=1MHz)
Parameter
Input capacitance ( CK, CK ) Input capacitance (A0~A10, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ31) Input capacitance(DM0 ~ DM3)
Symbol
CIN1 CIN2 CIN3 COUT CIN4
Min
3.0 3.0 3.0 3.0 3.0
Max
5 5 5 5 5
Unit
pF pF pF pF pF
- 34 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
AC CHARACTERISTICS
Parameter
CK cycle time CL=7 CL=6 CL=5 Symbol -20 (GF1000) Min Max 2.0 4.0 0.45 0.55 0.45 0.55 -0.35 0.35 -0.225 0.225 0.85 1.15 0.35 0.65 0.45 0.55 0.45 0.55 0.5 0.5 WL - 0.15 0 0.4 0.35 0.25 0.25 tCL/H min tHP-0.225 WL + 0.15 0.6 50 50 400
128M GDDR2 SDRAM
tCK tCH tCL tDQSCK tDQSQ tRPRE tRPST tDQSH tDQSL tIS tIH tDQSS tWPRES tWPST tWPRE tDS tDH tHP tQH tJ *1 tDC,ERR tR, tF
CK high width CK low width DQS out access time from CK Data strobe edge to Dout edge Read preamble Read postamble DQS in/out high level DQS in/out low level Address and Control input setup Address and Control input hold Write command to first DQS latching transition Write preamble setup time Write postamble Write preamble DQ_in and DM setup time to DQS DQ_in and DM hold time to DQS Clock half period Data output hold time from DQS Jitter over 1-6 clock cycles of CK Cycle to Cycle duty cycle error Rise and fall times of CK
-22 (GF900) Min Max 2.22 4.0 0.45 0.55 0.45 0.55 -0.45 0.45 -0.25 0.25 0.88 1.12 0.38 0.62 0.45 0.55 0.45 0.55 0.55 0.55 -
-25 (GF800) Min Max 2.5 4.0 0.45 0.55 0.45 0.55 -0.45 0.45 -0.28 0.28 0.9 1.1 0.4 0.6 0.45 0.55 0.45 0.55 0.6 0.6 -
Unit ns ns ns tCK tCK ns ns tCK tCK tCK tCK ns ns tCK ps tCK tCK ns ns ns ns ps ps ps
WL - 0.15 WL + 0.15 WL - 0.15 WL + 0.15 0 0.4 0.35 0.27 0.27 tCL/H min tHP-0.25 0.6 55 55 450 0 0.4 0.35 0.3 0.3 tCL/H min tHP-0.28 0.6 65 65 500
1. The cycle to cycle jitter and 2~6 cycle short term jitter.
Simplified Timing @ BL=4, CL=7, AL=0
0 CK, CK 1 2 6 7 8 9 10 11 12
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
NOP
NOP
Post CAS
Write A
NOP
NOP
DQS
RL = 7
DQ's
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DIN A0
DIN A1
DIN A2
DIN A3
WL = 1
WDQS
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
128M GDDR2 SDRAM
Note 1 : - The JEDEC DDR-II specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL7, BL4)
tHP 0 CK, CK 1 6 7 8 9
CS
DQS tDQSQ(max) tQH tDQSQ(max) DQ
Da0 Da1 Da2 Da3
COMMAND
READA
- 36 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
AC CHARACTERISTICS (I)
Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to any command Power down exit time Refresh interval time Symbol tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR tCDLR tCCD tMRD tDAL tXSA tPDEX tREF -20 (GF1000) Min Max 22 27 15 100K 8 5 7 5 5 4 2 4 12 20000 4tCK+tIS 7.8 -
128M GDDR2 SDRAM
-22 (GF900) Min Max 21 25 14 100K 8 5 7 5 5 4 2 4 12 20000 4tCK+tIS 7.8 -25 (GF800) Min Max 18 22 12 100K 7 4 6 4 4 4 2 4 10 20000 4tCK+tIS 7.8 -
Unit
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
- 37 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
PACKAGE DIMENSIONS (FBGA)
A1 INDEX MARK
128M GDDR2 SDRAM
13.0
13.0

0.8x11=8.8
0.10 Max A1 INDEX MARK
0.8
B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2
0.8
0.8x11=8.8
0.45 0.05
0.40
0.25 0.05 1.40 Max
0.40

Unit : mm
- 38 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
IBIS: I/V Characteristics for Input and Output Buffers
128M GDDR2 SDRAM
The termination resistor of the controller must be set to a appropriate value to satisfy output voltage level if the ODT of DRAM is on.
30 ohm Driver @ ODT OFF
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
35 30 25
Maximum
Iout(mA)
20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Typical Minimum
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 30 ohm@ODT OFF variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
0 -5 -10
Iout(mA)
-15 -20 -25 -30 -35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minumum Typical
Maximum
Vout(V)
Figure b : PulluP Charateristics
5. The 30 ohm@ODT OFF variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 30 ohm@ODT OFF variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
- 39 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum 0.0 6.3 11.8 16.4 20.4 23.5 25.9 27.5 28.4 29.0 29.3 29.5 29.7 29.9 30.0 30.1 30.2 30.3 30.3 30.4
Typical
0.0 4.4 8.1 11.2 13.8 15.9 17.4 18.4 19.0 19.4 19.7 19.8 20.0 20.1 20.2 20.2 20.3 20.4 20.4 20.5
Minimum 0.0 3.0 5.5 7.6 9.3 10.6 11.5 12.1 12.4 12.6 12.8 12.9 13.0 13.1 13.1 13.2 13.2 13.3 13.3 13.5
Typical
0.0 -3.6 -6.9 -9.7 -12.2 -14.3 -16.1 -17.4 -18.4 -19.1 -19.7 -20.3 -20.7 -21.1 -21.5 -21.8 -22.1 -22.4 -22.6 -22.9
Minimum 0.0 -2.5 -4.6 -6.6 -8.2 -9.6 -10.7 -11.6 -12.3 -12.8 -13.2 -13.6 -13.9 -14.2 -14.5 -14.7 -14.9 -15.1 -15.3 -15.5
Maximum 0.0 -4.9 -9.3 -13.3 -17.0 -20.1 -22.7 -24.6 -26.0 -27.1 -28.0 -28.7 -29.3 -29.8 -30.3 -30.7 -31.1 -31.4 -31.8 -32.1
Temperature (Tj) 50 C 100 C 0 C
Typical Minimum Maximum Vdd/Vddq
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 40 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
30 ohm Driver @ ODT 60 ohm Fix.
128M GDDR2 SDRAM
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT 60 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
60 50 40
Maximum Typical Minimum
Iout(mA)
30 20 10 0 -10 -20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 30 ohm@ODT 60 ohm Fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
20 10 0
Iout(mA)
-10 -20 -30 -40 -50 -60 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minumum Typical Maximum
Vout(V)
Figure b : PulluP Charateristics
5. The 30 ohm@ODT 60 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 30 ohm@ODT 60 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
- 41 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum -17.1 -9.0 -1.8 4.7 10.4 15.4 19.7 23.1 25.9 28.3 30.5 32.6 34.7 36.7 38.7 40.7 42.7 44.6 46.6 48.5
Typical
-14.4 -8.5 -3.2 1.6 5.8 9.5 12.7 15.3 17.5 19.6 21.5 23.3 25.1 26.8 28.6 30.3 32.0 33.7 35.4 37.1
Minimum -11.5 -7.1 -3.3 0.2 3.3 5.9 8.2 10.2 11.9 13.5 15.1 16.6 18.1 19.6 21.0 22.4 23.9 25.3 26.7 28.1
Typical
14.9 9.7 4.8 0.4 -3.7 -7.4 -10.8 -13.7 -16.4 -18.8 -21.0 -23.2 -25.3 -27.3 -29.4 -31.3 -33.3 -35.2 -37.1 -39.0
Minimum 11.9 8.1 4.6 1.3 -1.7 -4.4 -6.9 -9.2 -11.2 -13.2 -15.0 -16.8 -18.5 -20.2 -21.8 -23.5 -25.1 -26.6 -28.2 -29.8
Maximum 18.0 11.4 5.1 -0.8 -6.2 -11.2 -15.6 -19.4 -22.6 -25.6 -28.3 -30.9 -33.4 -35.8 -38.1 -40.4 -42.7 -44.9 -47.1 -49.3
Temperature (Tj) Typical Minimum Maximum Vdd/Vddq 50 C 100 C 0 C
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 42 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
30 ohm Driver @ODT 120 ohm Fix.
128M GDDR2 SDRAM
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 30 ohm@ODT 120 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
50 40
Maximum Typical Minimum
Iout(mA)
30 20 10 0 -10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 30 ohm@ODT 120 ohm Fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
10 0 -10
Iout(mA)
-20
Minumum
-30
Typical
-40
Maximum
-50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Vout(V)
Figure b : PulluP Charateristics
5. The 30 ohm@ODT 120 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 30 ohm@ODT 120 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
- 43 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum -8.6 -1.4 5.0 10.6 15.4 19.5 22.8 25.3 27.2 28.7 30.0 31.2 32.3 33.4 34.5 35.5 36.5 37.6 38.6 39.6
Typical
-7.2 -2.1 2.5 6.4 9.8 12.7 15.1 16.9 18.3 19.5 20.6 21.6 22.6 23.5 24.5 25.4 26.3 27.1 28.0 28.9
Minimum -5.8 -2.1 1.1 3.9 6.3 8.3 9.9 11.2 12.2 13.1 14.0 14.8 15.6 16.4 17.1 17.9 18.6 19.4 20.1 20.9
Typical
7.6 3.1 -0.9 -4.6 -7.9 -10.8 -13.4 -15.5 -17.3 -18.9 -20.4 -21.7 -23.0 -24.2 -25.4 -26.6 -27.7 -28.8 -29.9 -31.0
Minimum 6.1 2.9 0.1 -2.5 -4.9 -6.9 -8.8 -10.3 -11.7 -12.9 -14.1 -15.2 -16.2 -17.2 -18.1 -19.1 -20.0 -20.9 -21.8 -22.7
Maximum 9.1 3.4 -2.0 -6.9 -11.5 -15.5 -19.1 -21.9 -24.3 -26.3 -28.1 -29.7 -31.3 -32.7 -34.2 -35.5 -36.9 -38.2 -39.5 -40.7
Temperature (Tj) Typical Minimum Maximum Vdd/Vddq 50 C 100 C 0 C
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 44 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
45 ohm @ ODT OFF
128M GDDR2 SDRAM
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 45 ohm@ ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
35 30 25
Maximum Typical
Iout(mA)
20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minimum
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 45 ohm@ODT OFF variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
0 -5 -10
Iout(mA)
-15 -20 -25 -30 -35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minumum Typical
Maximum
Vout(V)
Figure b : PulluP Charateristics
5. The 45 ohm@ODT OFF variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 45 ohm@ODT OFF variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
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Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum 0.0 4.0 7.5 10.5 13.0 15.0 16.5 17.5 18.1 18.4 18.7 18.8 18.9 19.0 19.1 19.2 19.2 19.3 19.3 19.4
Typical
0.0 2.8 5.2 7.2 8.8 10.1 11.1 11.7 12.1 12.4 12.5 12.6 12.7 12.8 12.8 12.9 12.9 13.0 13.0 13.1
Minimum 0.0 1.9 3.5 4.9 5.9 6.8 7.3 7.7 7.9 8.0 8.1 8.2 8.3 8.3 8.4 8.4 8.4 8.5 8.5 8.6
Typical
0.0 -2.2 -4.2 -6.0 -7.5 -8.8 -9.8 -10.6 -11.2 -11.7 -12.1 -12.4 -12.7 -12.9 -13.1 -13.3 -13.5 -13.7 -13.8 -14.0
Minimum 0.0 -1.5 -2.8 -4.0 -5.0 -5.9 -6.6 -7.1 -7.5 -7.8 -8.1 -8.3 -8.5 -8.7 -8.8 -9.0 -9.1 -9.2 -9.4 -9.5
Maximum 0.0 -3.0 -5.7 -8.2 -10.4 -12.3 -13.9 -15.1 -15.9 -16.6 -17.1 -17.5 -17.9 -18.2 -18.5 -18.8 -19.0 -19.2 -19.4 -19.6
Temperature (Tj) Typical Minimum Maximum Vdd/Vddq 50 C 100 C 0 C
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 46 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
45 ohm Driver @ODT 120 ohm Fix.
128M GDDR2 SDRAM
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 45 ohm@ODT 120 ohm Fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
35 30 25
Maximum Typical Minimum
Iout(mA)
20 15 10 5 0 -5 -10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 45 ohm@ODT 120 ohm Fix variation pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
10 5 0 -5
Iout(mA)
-10 -15 -20 -25 -30 -35
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minumum Typical Maximum
Vout(V)
Figure b : PulluP Charateristics
5. The 45 ohm@ODT 120 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 45 ohm@ODT 120 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
- 47 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum -8.6 -3.7 0.7 4.6 8.0 11.0 13.5 15.4 16.9 18.2 19.3 20.5 21.5 22.6 23.6 24.6 25.6 26.6 27.6 28.6
Typical
-7.3 -3.7 -0.5 2.4 4.8 7.0 8.8 10.2 11.4 12.5 13.5 14.4 15.4 16.3 17.1 18.0 18.9 19.8 20.6 21.5
Minimum -5.8 -3.2 -0.9 1.2 2.9 4.4 5.7 6.8 7.7 8.6 9.4 10.7 10.9 11.6 12.4 13.1 13.8 14.6 15.3 16.0
Typical
7.6 4.6 1.8 -0.8 -3.2 -5.3 -7.1 -8.8 -10.2 -11.5 -12.7 -13.9 -15.0 -16.0 -17.1 -18.1 -19.1 -20.1 -21.1 -22.1
Minimum 6.1 3.9 1.9 0.0 -1.7 -3.2 -4.6 -5.8 -7.0 -8.0 -9.0 -9.9 -10.8 -11.7 -12.5 -13.4 -14.2 -15.0 -15.8 -16.7
Maximum 9.2 5.3 1.6 -1.8 -4.9 -7.8 -10.3 -12.4 -14.2 -15.8 -17.3 -18.6 -19.9 -21.2 -22.4 -23.7 -24.8 -16.0 -27.2 -28.3
Temperature (Tj) Typical Minimum Maximum Vdd/Vddq 50 C 100 C 0 C
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 48 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
60 ohm @ODT OFF
128M GDDR2 SDRAM
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 60 ohm@ODT OFF variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
16 14 12
Maximum
Iout(mA)
10 8 6 4 2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Typical Minimum
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 60 ohm@ODT OFF variation in drive pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
0 -2 -4
Iout(mA)
-6 -8 -10 -12 -14 -16 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minumum Typical
Maximum
Vout(V)
Figure b : PulluP Charateristics
5. The 60 ohm@ODT OFF variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 60 ohm@ODT OFF variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
- 49 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum 0.0 2.9 5.4 7.5 9.3 10.7 11.8 12.5 12.9 13.2 13.3 13.4 13.5 13.6 13.6 13.7 13.7 13.8 13.8 13.8
Typical
0.0 2.0 3.7 5.1 6.3 7.3 7.9 8.4 8.7 8.8 8.9 9.0 9.1 9.1 9.2 9.2 9.2 9.3 9.3 9.3
Minimum 0.0 1.4 2.5 3.5 4.2 4.8 5.2 5.5 5.7 5.8 5.8 5.9 5.9 5.9 6.0 6.0 6.0 6.0 6.1 6.2
Typical
0.0 -1.6 -3.1 -4.4 -5.5 -6.4 -7.2 -7.7 -8.2 -8.5 -8.8 -9.0 -9.2 -9.4 -9.5 -9.7 -9.8 -9.9 -10.1 -10.2
Minimum 0.0 -1.1 -2.1 -2.9 -3.7 -4.3 -4.8 -5.2 -5.5 -5.7 -5.9 -6.0 -6.2 -6.3 -6.4 -6.5 -6.6 -6.7 -6.8 -6.9
Maximum 0.0 -2.2 -4.2 -6.0 -7.6 -9.0 -10.1 -11.0 -11.6 -12.1 -12.4 -12.7 -13.0 -13.2 -13.5 -13.6 -13.8 -14.0 -14.1 -14.3
Temperature (Tj) Typical Minimum Maximum Vdd/Vddq 50 C 100 C 0 C
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 50 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
60 ohm Driver @ODT 120 ohm Fix.
128M GDDR2 SDRAM
1. The typical pulldown V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of Figure a. 2. The 60 ohm@ODT 120 ohm fix variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines the of the V-I curve of Figure a.
25 20 15
Maximum Typical Minimum
Iout(mA)
10 5 0 -5 -10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Figure a : Pulldown Charateristics
Vout(V)
3. The typical pullup V-I curve for DDR SDRAM devices will be within the inner bounding lines of the V-I curve of below Figure b. 4. The 60 ohm@ODT 120 ohm fix variation in drive pullup current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figrue b.
10 5 0
Iout(mA)
-5 -10 -15 -20 -25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Minumum Typical Maximum
Vout(V)
Figure b : PulluP Charateristics
5. The 60 ohm@ODT 120 ohm fix variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain to source voltage from 0 to VDDQ/2 6. The 60 ohm@ODT 120 ohm fix variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0 to VDDQ/2
- 51 -
Rev. 1.7 (Jan. 2003)
K4N26323AE-GC
Pulldown Current (mA) Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
128M GDDR2 SDRAM
Pullup Current (mA) Maximum -8.7 -4.9 -1.4 1.6 4.3 6.7 8.7 10.4 11.7 12.9 14.0 15.1 16.1 17.1 18.1 19.1 20.1 21.1 22.1 23.1
Typical
-7.3 -4.5 -2.0 0.3 2.3 4.1 5.6 6.9 8.0 9.0 9.9 10.8 11.7 12.6 13.5 14.2 15.2 16.1 16.9 17.8
Minimum -5.8 -3.7 -1.9 -0.2 1.2 2.5 3.6 4.6 5.5 6.3 7.0 7.8 8.5 9.3 10.0 10.7 11.4 12.1 12.8 13.6
Typical
7.6 5.2 2.9 0.8 -1.1 -2.9 -4.5 -5.9 -7.1 -8.3 -9.4 -10.5 -11.5 -12.5 -13.5 -14.5 -15.5 -16.4 -17.4 -18.3
Minimum 6.1 4.3 2.7 1.1 -0.3 -1.6 -2.8 -3.9 -4.9 -5.9 -6.8 -7.6 -8.5 -9.3 -10.1 -10.9 -11.7 -12.5 -13.3 -14.1
Maximum 9.2 6.1 3.2 0.5 -2.1 -4.4 -6.5 -8.3 -9.9 -11.3 -12.6 -13.9 -15.1 -16.3 -17.4 -18.5 -19.7 -20.8 -21.0 -23.0
Temperature (Tj) Typical Minimum Maximum Vdd/Vddq 50 C 100 C 0 C
Typical
Minimum Maximum
2.5V 2.4V 2.6V
The above characteristics are specified under best, worst and normal process variation/conditions
- 52 -
Rev. 1.7 (Jan. 2003)

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